In chip fabrication a plurality of integrated circuits are typically produced on one wafer and separated (singled) in a later step. A semiconductor disk that is produced and to be singled is referred to as a die.
The functionality of the semiconductor circuits that are integrated on the individual dies is usually checked prior to further processing (packaging) owing to the numerous parameters that fluctuate in semiconductor fabrication, which can influence component tolerances and so on, and owing to other stochastic influences. Only the semiconductor dies that correspond to the specified requirements are surrounded with a housing, for instance in TSOP or micro-PGA form. Only the pads on the semiconductor die that are intended to be available in normal operation are connected through to the outside, for instance by spider contacting. In contrast, the pads that are only needed for the above-mentioned testing steps are not connected through to the outside and are consequently protected against unintended contacting.
In modern packaging methods such as wafer level packaging (WLP), it is problematic that the pads on the semiconductor die that are needed for testing must be available for testing on the wafer level, that is to say prior to the singling of the silicon wafers, because the packaging still has to take place on the wafer level before the testing. In such methods, the packaging is first handled by attaching rewiring planes and connecting legs, for instance in the form of solder balls, on the silicon wafer, and then the functionality is tested on the wafer level. Accordingly, the terminal contacts that are needed for testing must be led to the outside and are thus exposed, without protection, to the risk of an unintended contacting even after the semiconductor dies are singled.
It is desirable to deactivate the terminal contacts that are led to the outside and provided only for testing, in order to prevent an unwanted activation of test functions or test routines of the integrated circuits on the semiconductor die.
It is accordingly an object of the invention to provide a semiconductor component that overcomes the above-mentioned disadvantages of the prior art devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component. The semiconductor component contains a main body having a surface and a plurality of pads including operating pads and test pads for connecting to electronic components integrated in the semiconductor component. A plurality of contact elements for conductively contacting the semiconductor component, the contact elements are disposed on the main body and are elevated relative to the surface resulting in elevated contact elements. Each of the elevated contact elements is allocated to one of the pads. A rewiring plane having a plurality of tracks conductively connects the pads to the contact elements that are elevated relative to the main body. An insulating layer is applied on the main side and covers the elevated contact elements allocated to the test pads while leaving the elevated contact elements allocated to the operating pads uncovered.
The terms semiconductor component and semiconductor die are hereinafter used synonymously.
The vertical contact elements are inventively characterized by being raised relative to the main side of the semiconductor die; that is, they extend orthogonally relative to the main side. As a result, when the semiconductor die is placed on a module or printed circuit board (PCB), only the raised contact elements touch the module or PCB, and conductive and/or mechanical contact can be produced.
All that is required for the fabrication of the semiconductor die that corresponds to the inventive principle is to insert an additional step, namely the application of an insulating layer on the main side of the semiconductor die. Care must be taken that the pads that are needed for test modes or test functions only are covered by the insulating layer and consequently protected against unintended contacting. On the other hand, the pads that are needed for normal operation of the semiconductor die are left uncovered.
The invention thus combines the advantages of wafer level packaging, namely cost savings, time savings, etc., which are particularly beneficial in mass production techniques, with the additional ability to protect the test pads at the semiconductor die against unwanted and unintended contacting after the testing on the wafer level and prior to further processing. The semiconductor die may be further processed by installation, e.g. soldering, onto a PCB.
The testing of specific functions of the circuits that are integrated on the semiconductor die on the wafer level can inventively occur even before the dies are singled but after the packaging step. The above described test pads can serve for charging the circuit that is integrated on the semiconductor die with specified signals, activating specified test functions, or making it possible to read test signals from the chip.
The insulating layer can be applied for a particularly small extra outlay with the aid of a solder stop mask.
In order to apply the insulating layer, a printing or plasma coating technique can be used. The insulating layer serves for electrically isolating the test pads, so that they can no longer be contacted externally. The material utilized for producing the insulating layer can be based on an epoxy, silicon, or other nonconductive compound.
In a preferred embodiment of the present invention, the vertical contact elements are bump-shaped.
The vertical contact elements can be constructed as bump-shaped elevations. The vertical contact elements can be constructed as solder balls.
According to another preferred embodiment of the invention, the vertical contact elements are disposed on the main side of the semiconductor die in a matrix configuration. One of the advantages of the matrix configuration of the vertical contact elements is that the grid (pitch) formed by the contacts can be relatively rough, while a relatively large number of vertical contact elements can be attached relative to the overall surface area of the semiconductor die. Furthermore, when placed on a PCB, the semiconductor die occupies only the chip area that it would occupy anyway.
In another preferred embodiment of the invention, the semiconductor die is constructed as a flip chip. In flip chip fabrication, the semiconductor dies are placed on a module or PCB face down. The installation can occur in a soldering process, for instance in a reflow soldering process.
In another preferred embodiment of the invention, the insulating layer is constructed as a solder stop layer. Applying such an insulating layer allows the inventive semiconductor dies to be produced for a particularly small added outlay specifically when the semiconductor die is to be further processed by reflow soldering.
In an additional preferred embodiment of the invention, the insulating layer is applied to the semiconductor die by serigraphy.
In an additional preferred embodiment of the invention, the insulating layer is a layer based on an epoxy material.
In another preferred embodiment of the invention, the insulating layer is realized as a silicon compound.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.